Selective formation of metal gate for dual gate oxide application

ABSTRACT

A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention relates to the fabrication of integrated circuitdevices, and more particularly, to a method of selectively forming oflow-voltage metal gate electrode in addition to forming a high-voltagepolysilicon gate electrode.

[0003] (2) Description of the Prior Art

[0004] Conventional methods of creating CMOS devices use gate electrodesof polysilicon that is deposited and patterned over a layer of gateoxide. In many applications the surface of the patterned and etchedlayer of polysilicon is salicided in order to meet requirements of lowcontact sheet resistivity. With the continued decrease in device anddevice feature dimensions, the polysilicon of the gate electrode is moreprone to depletion of the polysilicon, which results in a significantreduction in device performance. Polysilicon depletion results inincreased resistivity of the layer of polysilicon, which in turn resultsin an increase of the voltage drop across the polysilicon gate electrodewhen this electrode is reverse mode biased. To address and largelynegate this problem and in view of the fact that metal is a goodconductor, the industry in increasingly turning to the use of metal tocreate gate electrodes. Metal however is susceptible to migration tosurrounding regions under conditions of elevated temperature that canarise during the process of creating the CMOS device. The gate length ofCMOS devices is the distance between the source and the drain regions ofthe device where this distance extends underneath the gate electrode.With the continued decrease in device dimensions, the gate length forsub-micron devices has been decreased to 0.25 μm or less. For such smallgate length, the control of the Critical Dimension (CD) of thisparameter becomes a challenge. To address this aspect of metal gateelectrode design, the approach has been provided whereby a dummy gate isfirst created. This dummy gate uses a dielectric, such as silicondioxide or a polymer, for the body of the gate. The area surrounding thegate electrode is shielded by the deposition of a layer of for instanceoxide, an opening is created in this layer of oxide that aligns with thesurface of the gate electrode after which the dummy gate is removed. Theopening that is created in this manner can now be filled with newdielectrics first, for instance silicon dioxide or other high-kmaterial, and filled with metal. Polishing of the surface of thedeposited metal completes the creation of the sub-micron metal gateelectrode.

[0005] As previously stated, the integration of metal as the material ofchoice for the formation of high performance gate electrodes is requiredin order to reduce the depletion of gate polysilicon. This integrationof metal requires a gate replacement process. However, current logicapplication requires the use of different oxide thicknesses, typicallylimited to two thicknesses, for the creation of the gate dielectricunderlying the gate electrode. Core CMOS applications, which constitutethe majority of the CMOS devices that are being created, require highswitching speeds, which imposes the requirement of having a thin layerof gate dielectric. Also created however are Input/Output devices, whichare required to provide drive currents of relatively large values, whichimposes the requirement of having a relatively thick layer of gatedielectric. The requirement of simultaneously creating CMOS devices ofdifferent gate dielectric thicknesses may lead to two separate damasceneprocesses whereby each of these two processes provides for one thicknessof the gate dielectric. The invention addresses this concern andprovides a method for forming a metal gate electrode having a thin layerof gate dielectric, for high-performance application of CMOS devices.The low-voltage metal gate electrode of the invention is created overthe surface of a substrate over which high-voltage gate electrodes aresimultaneously created.

[0006] U.S. Pat. No. 6,087,231 (Xiang et al.) shows a process for a dualgate.

[0007] U.S. Pat. No. 6,159,782 (Xiang et al.), U.S. Pat. No. 5,960,270(Misra et al.) and U.S. Pat. No. 6,043,157 (Gardner et al.) revealprocesses for dual gates and dummy gates.

SUMMARY OF THE INVENTION

[0008] A principle objective of the invention is to provide a method forcreating a metal gate electrode having a thin layer of gate dielectricin an environment where polysilicon gates having different gatedielectric layers are present.

[0009] In accordance with the objectives of the invention a newprocessing sequence is provided for the creation of a metal gateelectrode. At least two polysilicon gate electrodes are provided overthe surface of a substrate, these polysilicon gate electrodes having arelatively thick layer of gate dielectric making these polysilicon gateelectrodes suitable for high-voltage applications. The two polysilicongate electrodes are divided into a first and a second gate electrode,both gate electrodes are imbedded in a layer of Intra Metal Dielectric(IMD). The first gate electrode is removed by applying a lift-offprocess to this first gate electrode, creating an opening in the layerof IMD. The second gate structure is shielded by a photoresist maskduring the removal of the first gate electrode. A metal gate electrodeis created in the opening created in the layer of IMD, using a thinlayer of gate dielectric.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIGS. 1 through 5 show a prior art method of creating a metal gateelectrode, as follows:

[0011]FIG. 1 shows a cross section of a semiconductor surface on thesurface of which has been formed a polysilicon gate structure, thepolysilicon gate structure is embedded in a layer of dielectric.

[0012]FIG. 2 shows a cross section of a semiconductor surface where thepolysilicon gate structure is removed from the semiconductor surface.

[0013]FIG. 3 shows a cross section of a semiconductor surface from thesurface of which the polysilicon gate structure has been removed, alayer of high-k dielectric and a layer of metal have been deposited.

[0014]FIG. 4 shows a cross section of a semiconductor surface after thedeposited layers of high-k dielectric and metal have been polished downto the surface of the layer of dielectric, forming a damascene metalgate structure.

[0015]FIG. 5 shows a cross section of a semiconductor surface after thedeposited layers of high-k dielectric and metal have been etched,forming an etch back metal gate structure.

[0016]FIGS. 6 through 9 describe prior art methods of creatingpolysilicon gate electrodes having layers of gate dielectric ofdifferent thicknesses, as follows:

[0017]FIG. 6 shows a cross section of two polysilicon gate electrodescreated over the surface of a substrate.

[0018]FIG. 7 shows a cross section where the polysilicon and the gatedielectric of the two gate electrodes have been removed.

[0019]FIG. 8 shows a cross section after a thin layer of gate dielectrichas been universally deposited, the thin layer of gate dielectricoverlying a first gate electrode is shielded by the deposition of alayer of developed photoresist.

[0020]FIG. 9 shows a cross section where the layer of thin gatedielectric has been removed in accordance with the photoresist mask ofFIG. 8, as relatively thick layer of gate dielectric has been deposited,the photoresist mask has been removed from the surface of the substrate.

[0021] The invention is described using FIGS. 10 through 13, as follows:

[0022]FIG. 10 shows a cross section of a semiconductor surface on thesurface of which has been formed a first, dummy polysilicon gateelectrode and a second polysilicon gate electrode, the gate electrodesare embedded in a main layer of dielectric.

[0023]FIG. 11 shows a cross section of the semiconductor surface of FIG.10 after a patterned layer of photoresist has been created overlying themain layer of dielectric shielding the second polysilicon gateelectrode, the first polysilicon gate structure is being removed fromthe semiconductor surface, creating an opening in the main layer ofdielectric.

[0024]FIG. 12 shows a cross section of the semiconductor surface of FIG.11 after the patterned layer of photoresist has been removed from abovethe main layer of dielectric. A layer of high-k dielectric has beendeposited over the surface of the main layer of dielectric including theinside surfaces of the opening created in the main layer of dielectric,further including the surface of the second polysilicon gate electrode,a layer of metal has been deposited over the surface of the high-kdielectric.

[0025]FIG. 13 shows a cross section of the semiconductor surface of FIG.12 after the layer of high-k dielectric and the layer of metal have beenremoved from the surface of the main layer of dielectric, leaving inplace a metal gate electrode overlying a relatively thin, high-k layerof gate dielectric in addition to a polysilicon gate electrode overlyinga relatively thick layer of gate dielectric.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] A brief overview of typical prior art processing steps that areapplied for the creation of a metal gate electrode will be presentedfirst. Referring to FIG. 1 there is shown a cross section of asemiconductor surface 10, preferably the surface of a monocrystallinesilicon substrate, on the surface of which a gate electrode 12 has beencreated. Isolation regions 14 have been formed in the surface of surface10 in order to define and electrically isolate active surface regions inthe surface of layer 10. After the regions 14 of for instance FieldOxide (FOX) or of Shallow Trench Isolation (STI) have been created, alayer 16 of pad oxide is created over the surface of substrate 10 bymethods of either Chemical Vapor Deposition (CVD) or by exposing thesurface of substrate 10 to an oxidizing environment under elevatedtemperatures.

[0027] After the layer 16 of pad oxide has been created, a dummy gateelectrode layer 18 is formed by depositing polysilicon. Conventionalmethods of photolithography and anisotropic etching are applied to thelayers 16 of pad oxide and 18 of polysilicon to form the patternedlayers 16 and 18 that are shown in cross section in FIG. 1.

[0028] Lightly Doped (LDD) source implant 20 and drain implant 22 areperformed next that are self-aligned with the gate structure 16/18 andthat extend laterally along the surface of substrate 10 in the immediateadjacency of the gate electrode structure 16/18. Dependent on the typeof device that is being created, that is a NMOS or a PMOS device, theseimplants are either n-type or p-type impurities.

[0029] Gate spacers 24 are typically formed using materials such assilicon nitride, silicon oxide, BSG, PSG, polysilicon, other materialspreferably of a dielectric nature, CVD oxide formed from a TEOS source.Often used materials are amorphous materials that inhibit the depositionof epitaxial silicon thereupon. Spacers can for instance be formed byfirst depositing a layer of silicon oxide after which an anisotropic RIEprocedure is applied using CHF₃, CF₄ and H₂ as an etchant. Gate spacers24 typically have a thickness of between 300 and 2000 Angstrom.

[0030] Source region 26 and drain region 28 are next formed in thesurface of substrate 10, self-aligned with the gate spacers 24 of thegate structure 16/18. For NMOS devices, the implants for the source anddrain regions use n-type impurities such as arsenic or phosphorous, forPMOS devices a p-type implant such as indium or boron can be used.

[0031] The surface of the gate electrode structure 16/18 can next besalicided in order to reduce the contact resistance with the gateelectrode. This saliciding of the surface of the gate electrode at thesame time salicides the surface regions of the source and drain regionsof the gate electrode.

[0032] Layer 30 of the gate electrode has been highlighted as being asalicided layer since the process of salicidation can be performedsimultaneously with saliciding the source and drain contact points ofthe gate structure. For the creation of layer 30 tungsten can beapplied.

[0033] Further shown in cross section in FIG. 1 is the deposition of ablanket layer 32 over the dummy gate electrode 12 and the exposedsurface of substrate 10, thereby including the surface of the isolationregions 14. This layer 32 of dielectric, preferably containing silicondioxide, is deposited to a thickness such that the surface of layer 32is at least equal to the surface of the salicided layer 30 on thesurface of the dummy gate electrode 16/18. Dielectric that has beendeposited exceeding this height can be removed by Chemical MechanicalPolishing or by methods of etching. Layer 30 of salicided material is ofhigher hardness than the surface of the layer 32 of dielectric that isbeing polished and can therefore serve as a stop layer for the CMPprocess.

[0034]FIG. 2 shows the removal 34 of the dummy gate electrode comprisingthe layers 16, 18 and 30 from between the gate spacers 24, forming anopening 35 between the gate spacers 24. The dummy gate can be removedusing conventional methods of etch. The layer 16 of pad oxide can beremoved using CHF₃/CF₄ or HF etch chemistry.

[0035] Referring now to FIG. 3, a layer 36 of gate dielectric isdeposited over the surface of layer 32 and the inside surfaces ofopening 35 that has been created between gate spacers 24. Over thesurface of the dielectric layer 36 is deposited a layer 38 of metal thatis deposited to a thickness sufficient to fill opening 35. The gateelectrode can further comprise a barrier layer, copper interconnectsshould be encapsulated by at least one diffusion barrier to preventdiffusion into the silicon dioxide layer. Silicon nitride is a diffusionbarrier to copper, the prior art teaches that copper interconnectsshould not lie on a silicon nitride layer because it has a highdielectric constant compared with silicon dioxide. The high dielectricconstant when applied with interconnects causes an undesired increase incapacitance between the interconnects and the substrate. For the case ofa metal gate electrode, a high-k dielectric is required for the metalstructure making silicon nitride a desirable dielectric for copperapplications.

[0036] Referring to FIG. 4, this cross section shows the results thatare obtained by polishing layers 38 and 36 down to the surface of thelayer 32 of dielectric.

[0037] The metal gate electrode that is shown in cross section in FIG. 4provides a metal gate with a damascene type plug. As an alternateprocess, the surface of the metal gate electrode can be extended as isshown in cross section in FIG. 5. The metal gate structure that is shownin cross section in FIG. 4 is referred to as a damascene metal gatestructure, the metal gate structure that is shown in cross section inFIG. 5 is referred to as an etch back metal gate structure.

[0038]FIGS. 6 through 9 briefly highlight the conventional art method ofcreating polysilicon gate electrodes having different thicknesses forthe layer of gate dielectric, as follows:

[0039]FIG. 6 shows a cross section of the following new elements:

[0040]70 and 72, two polysilicon gate electrodes created over thesurface of a substrate

[0041]73, the layer of polysilicon that forms the main body of gateelectrodes 72 and 74

[0042]74, the salicided top surface of gate electrodes 72 and 74

[0043]76, the layers of gate dielectric underlying gate electrodes 72and 74 and forming part of these gate electrodes

[0044]FIG. 7 shows a cross section where the polysilicon and the gatedielectric of the two gate electrodes 72 and 74 have been removed,creating openings 78 and 80 in the layer 32 of dielectric.

[0045]FIG. 8 shows a cross section after a thin layer 82 of gatedielectric has been universally deposited. After the thin layer 82 ofgate dielectric has been deposited, the first gate electrode 78 isshielded by the deposition of a patterned and developed layer 84 ofphotoresist.

[0046]FIG. 9 shows a cross section where the layer 82 of thin gatedielectric has been removed in accordance with the photoresist mask 84of FIG. 8. A relatively thick layer 86 of gate dielectric has beendeposited, the photoresist mask 84 has been removed from the surface ofthe substrate.

[0047] At this point in the creation of the two gate electrodes, layersof gate dielectric of different thickness have been provided overlyingthe inside surfaces of openings 78 and 80. It is from this clear that,by filling openings 78 and 80 with polysilicon, two different gateelectrodes are being formed with layers of gate dielectric that aredifferent and that are determined by the thickness of the deposition ofthe layers 82 and 86 of gate dielectric material.

[0048] The processing steps of the invention will now be explained indetail using FIGS. 10 through 13. It must thereby be remembered that itis the objective of the invention to create, overlying the surface of asubstrate, a high-voltage polysilicon gate electrode (having arelatively thick layer of gate dielectric) and a low-voltage metal gateelectrode (having a relatively thin layer of gate dielectric).

[0049] Referring to FIG. 10 there is shown a cross section of asemiconductor surface 10, preferably the surface of a monocrystallinesilicon substrate, on the surface of which polysilicon gate electrodes12 and 42 have been created. The objective of the invention is to createa high voltage I/O CMOS device and a low voltage metal CMOS device. Forthis purpose, gate electrode 42 will be created as a high voltage I/OCMOS device while gate electrode in location 12 will be created as a lowvoltage metal CMOS device.

[0050] Isolation regions 14 have been formed in the surface of surface10 in order to define and electrically isolate active surface regions inthe surface of layer 10. After the regions 14 of for instance FieldOxide (FOX) or of Shallow Trench Isolation (STI) have been created, alayer 16 of pad oxide is created over the surface of substrate 10 usingmethods of either Chemical Vapor Deposition (CVD) or by exposing thesurface of substrate to an oxidizing environment under elevatedtemperatures. Typically, a blanket pad oxide can be formed to athickness of about 150 Angstrom through a thermal oxidation method at atemperature of about 900 degrees C. for a time period of about 10 to 20minutes. The layer 16 of thin oxide can also be created by applyingconventional deposition technology and can, for instance, be depositedusing PECVD procedures at a temperature of between about 350 and 450degrees C. to a thickness between about 125 and 150 Angstrom using TEOSor SiH₄ as a source.

[0051] Gate electrode 42 that is shown in cross section in FIG. 10 hasbeen created as a high voltage I/O current drive CMOS device and hastherefore been provided with a relatively thick layer 16 of pad oxide,that is in the range between about 300 and 600 Angstrom and morepreferably about 450 Angstrom.

[0052] After the layer 16 of pad oxide has been created, a dummy gateelectrode layer 18 and the polysilicon layer 46 are formed by depositingpolysilicon to a thickness between about 12000 and 3000 Angstrom overthe layer 16 of pad oxide. Conventional methods of photolithography andanisotropic etching are applied to the layers of pad oxide and ofpolysilicon to form the patterned layers 16, 18 and 46 that are shown incross section in FIG. 10. Layers 16 and 18 are part of gate electrode12, layers 16 and 46 are part of the polysilicon gate electrodes 42.

[0053] Lightly Doped (LDD) source implants 20 and drain implants 22 areperformed next that are self-aligned with the gate structures 12 and 42,these implants extend laterally along the surface of substrate 10 in theimmediate adjacency of the gate electrode structures 12 and 42.Dependent on the type of device that is being created, that is a NMOS ora PMOS device, these implants are n-type or p-type impurities that areimplanted at an energy of between about 1 KeV and 100 KeV and a densitybetween about 1-E12 atoms/cm² and 5E15 atoms/cm². Spacers 24 are nextformed on the sidewalls of the gate structures by a blanket depositionof a suitable gate spacer material followed by an isotropic etch back ofthe deposited gate spacer material. Gate spacers 24 typically have athickness of between 300 and 2000 Angstrom.

[0054] Source region 26 and drain region 28 are next formed in thesurface of substrate 10. For NMOS devices, the implant for the sourceand drain regions uses n-type impurities such as arsenic or phosphorous,for PMOS devices a p-type implant such as indium or boron can be used.Implant for the source and drain regions are typically performed at anenergy of between about 1 KeV and 100 KeV and an impurity concentrationof between about 1E15 atoms/cm² and 8E15 atoms/cm² Impurity implantsthat have been performed into the surface of the substrate for thecreation of source and drain regions can further be activated (furtherdriven into the surface of the substrate) by performing a rapid thermalanneal after the implant has been completed.

[0055] The surface of the gate electrode structures 12 and 42 can nextbe salicided in order to reduce the contact resistance with the gateelectrode. This saliciding of the surface of the gate electrodes 12 and42 also salicides the surface regions of the source (26) and drain (28)regions of the gate electrodes 12 and 42. As an example can be cited theformation of a layer of titanium salicide on the surface of the gateelectrodes 12 and 42. A layer of titanium can be deposited over thesurface of the substrate to a thickness between about 300 to 600Angstrom at a temperature of 25 to 300 degrees C. using either rf.sputtering or CVD techniques. A first anneal is performed to the layerof titanium to convert the titanium to the salicided stage. The firstanneal is a rapid thermal annealing in a temperature range of betweenabout 600 and 800 degrees C. for a time between about 20 and 40 secondsin a nitrogen ambient. The unreacted titanium is then removed from thesurface with an etchback using a wet NH₄OH and H₂O₂ solution. A CVDtitanium can also be etched using a dry CF₄ and oxygen environment. Asecond anneal can be applied to transform the layer of titanium silicide(TiSi₂) over the gate electrode region from the high resistivity phaseto the low resistivity phase can be applied. The second anneal is arapid thermal anneal in a temperature range of between about 800 and 900degrees C. for a time between 20 and 40 seconds in an N₂ ambient.

[0056] For the creation of layer 30 and layer 44 tungsten can also beapplied. A layer of tungsten can be selectively formed on the surface ofthe gate electrodes 12 and 42 by CVD deposition at a temperature betweenabout 300 degrees C. and 500 degrees C. and a pressure between about 50mTorr and 500 mTorr using as source gasses SiH₄ and WF₄ with a flowratio of between about 0.1 and 5.0 sccm between these two source gasses.

[0057] Further shown in cross section in FIG. 10 is the deposition of ablanket layer 32 of dielectric over the dummy gate electrode 12 and thegate electrode 42 and the exposed surface of substrate 10, therebyincluding the surface of the isolation regions 14. This layer 32 ofdielectric, preferably containing silicon dioxide, is deposited to athickness such that the surface of layer 32 is at least equal to thesurface of the gate structures 12 and 42. Dielectric 32 that has beendeposited exceeding this height can be removed by Chemical MechanicalPolishing or by methods of etching.

[0058] For layer 32 of dielectric the preferred dielectrics are silicondioxide (doped or undoped), silicon oxynitride, parylene or polyimide,spin-on-glass, plasma oxide or LPCVD oxide.

[0059] It must be noted in the cross section that is shown in FIG. 10that the layer 16 of gate dielectric, specifically as this layer relatesto gate electrode 42, is already formed to the desired thickness so thatgate electrode 42 can function as a high-voltage CMOS device.

[0060]FIG. 11 shows the deposition of a layer 50 of photoresist, layer50 has been patterned and developed leaving in place a shielding layerof photoresist overlying the gate structure 42. The process ofdeposition and developing the layer 50 of photoresist uses conventionalmethods of photolithography and masking. Layer 50 of photoresist can beetched by applying O₂ plasma and then wet stripping by using H₂SO₄, H₂O₂and NH₄OH solution. The photoresist that is removed from the surface ofthe layer 32 of dielectric exposes gate electrode 12.

[0061]FIG. 11 further shows the removal 34 of the dummy gate electrode12 comprising the layers 16, 18 and 30 from between the gate spacers 24,forming an opening 35 between the gate spacers 24 of gate electrode 12.The dummy plug can be removed using conventional methods of etch, usingchlorine as a reactant gas to etch the salicided layer 30 and thepolysilicon layer 18, assuring that the etch for the removal of thesetwo layers is highly selective to the silicon dioxide of the surroundinglayer 32 of dielectric. The layer 16 of pad oxide can be removed usingCHF₃/CF₄ or HF etch chemistry. Layer 16 of pad oxide can also be etchedusing Ar/CF₄ as an etchant at a temperature of between about 120 and 160degrees C. and a pressure of between about 0.30 and 0.40 Torr for a timeof between about 33 and 39 seconds using a dry etch process.

[0062] Referring now to FIG. 12, a layer 36 of high-k gate dielectric isdeposited over the surface of layer 32 of dielectric and the insidesurfaces of opening 35 that has been created between gate spacers 24 ofgate electrode 12. Optionally and prior to the deposition of a layer 36of high-k dielectric, a layer of gate oxide can be formed on the bottomof the opening that is created in the layer of dielectric by the removalof the dummy gate. Layer 36 of high-k dielectric is preferably depositedto a thickness between about 50 and 150 Angstrom and more preferably toa thickness of about 100 Angstrom.

[0063] Over the surface of the high-k dielectric layer 36 is deposited alayer 38 of metal that is deposited to a thickness sufficient to fillopening 35. The metal that is used for layer 38 is composed of a metalselected from the group comprising titanium, tungsten, copper oraluminum or alloys thereof and can be deposited using methods of PlasmaEnhanced Chemical Vapor Deposition (PECVD), sputtering or Chemical VaporDeposition (CVD). The gate electrode can further comprise a barrierlayer of a material selected from the group comprising titanium nitride,tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is morepreferably formed from TiN. Copper interconnects should be encapsulatedby at least one diffusion barrier to prevent diffusion into the silicondioxide layer. Silicon nitride is a diffusion barrier to copper, theprior art teaches that copper interconnects should not lie on a siliconnitride layer because it has a high dielectric constant compared withsilicon dioxide. The high dielectric constant when applied withinterconnects causes an undesired increase in capacitance between theinterconnects and the substrate. For the case of a metal gate electrode,a high-k dielectric is required for the metal structure making siliconnitride a desirable dielectric for copper applications. As examples ofmaterials that can be used for layer 36 can be cited Si₃N₄ and Al₂O₃which are dielectric materials with a high dielectric constant(Si₃N₄-7.4, Al₂O₃-8.5), also oxide-nitride-oxide (ONO), Si₂O and otherhigh dielectric constant material such as tantalum pentoxide (TaO₅),titanium oxide (TiO₂), zirconium oxide (ZrO₂), tantalum oxide (Ta₂O₅),barium titanium oxide (BaTiO₃) and strontium titanium oxide (SrTiO₃).

[0064] It must be noted from the cross section that is shown in FIG. 12that the layer 36 of high-k gate dielectric and the layer 38 of metalcan be deposited in the same processing chamber, in-situ and withoutbraking the operational vacuum.

[0065] Referring to FIG. 13, this cross section shows the results thatare obtained by polishing the surface of layers 38 and 36 down to thesurface of the layer 32 of dielectric. Metal gate electrode 52 has atthis time been created on the surface of substrate 10 and embedded inthe layer 32 of Intra Metal Dielectric. The transition from the crosssection that is shown in FIG. 12 to the cross section that is shown inFIG. 13 is achieved by removing excess high-k dielectric layer 36 andthe excess metal 38 deposited over the surface of layer 32 of dielectricfrom the surface of layer 32. This is accomplished by applying ChemicalMechanical Polishing (CMP) to the surface of layers 38 and 36, using thesurface of layer 32 as the stop layer.

[0066] It is at this point of value to make the observations that thethickness of layer 36 of high-k dielectric can be independentlycontrolled and can therefore be selected to be a relatively thin layerof dielectric. This allows for the creation of a metal gate electrodethat can be used for high-performance applications, since this type of agate typically is required to provide fast switching speeds. Thepreferred thickness of layer 36 of the invention is between about 50 and150 Angstrom and more preferably about 100 Angstrom. Further, gateelectrode 42 has, during the creation of the I/O metal gate 52, not beenaffected.

[0067] Although the invention has been described and illustrated withreference to specific illustrative embodiments thereof, it is notintended that the invention be limited to those illustrativeembodiments. Those skilled in the art will recognize that variations andmodifications can be made without departing from the spirit of theinvention. It is therefore intended to include within the invention allsuch variations and modifications which fall within the scope of theappended claims and equivalents thereof.

What is claimed is:
 1. A method of creating metal gate electrodes andpolysilicon gate electrodes over the surface of a substrate, said metalgate electrodes and said polysilicon gate electrodes having gatedielectric layers of different thicknesses, comprising the steps of:providing a semiconductor substrate, at least one first and one secondgate electrode structures having been provided over the surface of saidsubstrate, said at least one first and said at least one second gateelectrode having been provided with a gate electrode body having asurface further having sidewalls which are essentially perpendicular tothe surface of said substrate, said at least one first and said at leastone second gate electrode having been provided with Lightly DopedDiffusion impurity implants into the surface of said substrate that areself-aligned with the body of said at least one first and said at leastone second gate electrode, said at least one first and said at least onesecond gate electrode having been provided with gate spacers over saidsidewalls of said at least one first and said at least one second gateelectrode, said at least one first and said at least one second gateelectrode having been provided with source and drain impurity implantsinto the surface of said substrate that are self-aligned with the gatespacers of said at least one first and said at least one second gateelectrode, said at least one first and said at least one second gateelectrode being imbedded in a layer of Intra Metal Dielectric (IMD),said layer of IMD having been polished down to the surface of the bodyof said at least one first and said at least one second gate electrode,said at least one first and said at least one second gate electrodebeing electrically isolated from each other by a region of FieldIsolation that has been created in the surface of said substrate;creating a photoresist mask overlying said at least one second gateelectrode; removing said dummy gate electrode from between said gatespacers of said at least one first gate electrode, creating at least oneopening in said layer of IMD; depositing a layer of high-k dielectricover the surface of said layer of IMD, including inside surfaces of saidat least one opening created in said layer of IMD; depositing a layer ofmetal over the surface of said layer of high-k dielectric, filling saidat least one opening created in said layer of IMD; and removing saidlayer of high-k dielectric and said layer of metal from above thesurface of said layer of IMD, leaving said layer of high-k dielectric inplace over inside surfaces of said at least one opening created in saidlayer of IMD, further leaving said layer of metal in place over thesurface of said layer of high-k dielectric inside said at least oneopening created in said layer of IMD.
 2. The method of claim 1 whereinsaid layer of high-k dielectric deposited over the surface of said layerof IMD is deposited to a thickness of between about 50 and 150 Angstromand more preferably to a thickness of about 100 Angstrom.
 3. The methodof claim 1 wherein said layer of high-k dielectric deposited over thesurface of said layer of IMD is selected from the group consisting ofsilicon nitride (Si₃N₄) and aluminum oxide (Al₂O₃) andoxide-nitride-oxide (ONO) and silicon oxide (Si₂O) and tantalumpentoxide (TaO₅) and titanium oxide (TiO₂) and zirconium oxide (ZrO₂)and tantalum oxide (Ta₂O₅) and barium titanium oxide (BaTiO₃) andstrontium titanium oxide (SrTiO₃).
 4. The method of claim 1 wherein saidlayer of metal deposited over the surface of said layer of high-kcomprises a metal selected from the group consisting of titanium andtungsten and copper and aluminum and alloys thereof.
 5. The method ofclaim 1 wherein said gate electrode body of said at least one first gateelectrode comprises a patterned layer of gate dielectric created overthe surface of said substrate over which a patterned layer ofpolysilicon has been created.
 6. The method of claim 1 wherein said gateelectrode body of said at least one second gate electrode comprises apatterned layer of gate dielectric deposited to a thickness betweenabout 300 and 600 Angstrom and more preferably about 450 Angstrom overwhich a patterned layer of polysilicon has been created.
 7. The methodof claim 1 with an additional processing step of depositing a layer ofbarrier material over the surface of said layer of IMD, said additionalprocessing step being performed prior to depositing said high-kdielectric over the surface of said layer of IMD, said layer of barriermaterial being removed from the surface of said layer of IMD as anextension of said step of removing said layer of high-k dielectric andsaid layer of metal from above the surface of said layer of IMD, leavingsaid barrier material in place overlying inside surfaces of said atleast one opening created in said layer if IMD.
 8. The method of claim 1with additional processing steps of saliciding contact surfaces to saidat least one first and said at least one second gate electrode, saidsalicidation being performed prior to said providing gate spacers oversaid sidewalls of said at least one first and said at least one secondgate electrode.
 9. A method of creating at least one high voltagepolysilicon gate electrode and one low voltage metal gate electrode overthe surface of a substrate, comprising the steps of: providing asemiconductor substrate; creating a region of Field Isolation in thesurface of said substrate, thereby separating an active surface regionin the surface of said substrate over which said at least onehigh-voltage gate electrode is to be created from an active surfaceregion in the surface of said substrate over which said at least onelow-voltage metal gate electrode is to created; creating a layer of gateoxide over the surface of said substrate, said layer of gate oxidehaving a thickness between about 300 and 600 Angstrom and morepreferably about 450 Angstrom; depositing a layer of polysilicon overthe surface of said layer of gate oxide; patterning and etching saidlayer of polysilicon and said layer of pad oxide, creating patternedlayers of polysilicon and gate oxide having sidewalls further having asurface for said at least one high voltage polysilicon gate electrodeand said at least one low voltage metal gate electrode over the surfaceof a substrate; performing Lightly Doped Diffusion impurity implantsinto the surface of said substrate self-aligned with said patternedlayers of polysilicon and gate oxide for said at least one high voltagepolysilicon gate electrode and said at least one low voltage metal gateelectrode; creating gate spacers over sidewalls of said patterned layersof polysilicon and gate oxide for said at least one high voltagepolysilicon gate electrode and said at least one low voltage metal gateelectrode; performing source and drain impurity implants into thesurface of said substrate self-aligned with said gate spacers createdover sidewalls of said patterned layers of polysilicon and gate oxidefor said at least one high voltage polysilicon gate electrode and saidat least one low voltage metal gate electrode; saliciding the surface ofsaid source and drain impurity implants and the surface of saidpatterned layers of polysilicon for said at least one high voltagepolysilicon gate electrode and said at least one low voltage metal gateelectrode, creating salicided contact surfaces to said at least one highvoltage polysilicon gate electrode and said at least one low voltagemetal gate electrode; depositing a layer of Intra Metal Dielectric overthe surface of said substrate, including the salicided contact surfacesand the surface of said gate spacers created over sidewalls of saidpatterned layers of polysilicon and gate oxide for said at least onehigh voltage polysilicon gate electrode and said at least one lowvoltage metal gate electrode; polishing said deposited layer of IntraMetal Dielectric down to said salicided contact surfaces of saidpatterned and salicided layers of polysilicon for said at least one highvoltage polysilicon gate electrode and said at least one low voltagemetal gate electrode; creating a photoresist mask overlying the surfaceof said layer of Intra Metal Dielectric, said photoresist mask overlyingsaid at least one high voltage polysilicon gate electrode; removing saidat least one low voltage gate electrode from between said gate spacersformed over sidewalls of said patterned layers of polysilicon and gateoxide for said at least one low voltage polysilicon gate electrode,creating at least one opening in said layer of IMD; depositing a layerof high-k dielectric over the surface of said layer of IMD, includinginside surfaces of said at least one opening created in said layer ofIMD; depositing a layer of metal over the surface of said layer ofhigh-k dielectric, filling said at least one opening created in saidlayer of IMD; and removing said layer of high-k dielectric and saidlayer of metal from above the surface of said layer of IMD, leaving saidlayer of high-k dielectric in place over inside surfaces of said atleast one opening created in said layer of IMD, further leaving saidlayer of metal in place over the surface of said layer of high-kdielectric inside said at least one opening created in said layer ofIMD.
 10. The method of claim 9 wherein said layer of high-k dielectricdeposited over the surface of said layer of IMD is deposited to athickness of between about 50 and 150 Angstrom and more preferably to athickness of about 100 Angstrom.
 11. The method of claim 9 wherein saidlayer of high-k dielectric deposited over the surface of said layer ofIMD is selected from the group consisting of silicon nitride (Si₃N₄) andaluminum oxide (Al₂O₃) and oxide-nitride-oxide (ONO) and silicon oxide(Si₂O) and tantalum pentoxide (TaO₅) and titanium oxide (TiO₂) andzirconium oxide (ZrO₂) and tantalum oxide (Ta₂O₅) and barium titaniumoxide (BaTiO₃) and strontium titanium oxide (SrTiO₃).
 12. The method ofclaim 9 wherein said layer of metal deposited over the surface of saidlayer of high-k comprises a metal selected from the group consisting oftitanium and tungsten and copper and aluminum and alloys thereof. 13.The method of claim 9 wherein said at least one high voltage polysilicongate electrode comprises a patterned layer of gate dielectric depositedto a thickness between about 300 and 600 Angstrom and more preferablyabout 450 Angstrom over which a patterned and salicided layer ofpolysilicon has been created.
 14. The method of claim 9 with anadditional processing step of depositing a layer of barrier materialover the surface of said layer of IMD, said additional processing stepbeing performed prior to depositing said high-k dielectric over thesurface of said layer of IMD, said layer of barrier material beingremoved from the surface of said layer of IMD as an extension of saidstep of removing said layer of high-k dielectric and said layer of metalfrom above the surface of said layer of IMD, leaving said barriermaterial in place overlying inside surfaces of said at least one openingcreated in said layer if IMD.